This invention relates to a semiconductor integrated circuit device and a semiconductor memory, and more particularly to a variable potential generating circuit for selectively generating a plurality of different potentials by use of a current-scaling type digital/analog (D/A) converter circuit and can be applied to a multistage voltage generating circuit for data writing and data erasing in a nonvolatile semiconductor memory, for example.
A variable potential generating circuit is used to generate a plurality of different potentials in a semiconductor integrated circuit device and supply the generated potential to an internal circuit. When a D/A converter circuit is used in part of the variable potential generating circuit, a resistive potential dividing type D/A converter as shown in FIG. 1 or a current-scaling type D/A converter as shown in FIG. 2 is conventionally used, for example.
The resistive potential dividing type D/A converter shown in FIG. 1 includes dividing resistors R.sub.0 to R.sub.16, switching elements S.sub.1 to S.sub.16, operational amplifier 11, P-channel MOS (PMOS) transistor 12 and decoder circuit 13. The inverting input terminal (-) of the operational amplifier 11 is applied with a reference potential V.sub.R. The source of the PMOS transistor 12 is connected to a Vcc node to which a power supply potential Vcc is applied, and the gate thereof is connected to the output terminal of the operational amplifier 11. The operational amplifier 11 and PMOS transistor 12 are used for feedback control. The dividing resistors R.sub.0 to R.sub.16 are serially connected between the drain of the PMOS transistor 12 and a Vss node to which a ground potential Vss is applied. The switching elements S.sub.1 to S.sub.16 are connected between the voltage dividing nodes of the dividing resistors R.sub.0 to R.sub.16 and the non-inverting input terminal (+) of the operational amplifier 11. The decoder circuit 13 is provided for each of the switching elements S.sub.1 to S.sub.16 to decode digital signals A.sub.0 to A.sub.3 and control the switching states of the switching elements S.sub.1 to S.sub.16 according to the decoded outputs. In FIG. 1, the digital signals A.sub.0, A.sub.1, A.sub.2, A.sub.3 are "0101", the switching element S.sub.11 is selected and set in the ON state, and the switching elements S.sub.1 to S.sub.10 and S.sub.12 to S.sub.16 are non-selected and set in the OFF state. A variable output potential Vout corresponding to the switching states of the switching elements S.sub.1 to S.sub.16 is obtained from the variable potential output node connected to a connection node of the drain of the PMOS transistor 12 and the resistor R.sub.0.
In the resistive voltage dividing type D/A converter circuit, the relation of Vout=(R.sub.T /R)V.sub.R can be obtained if the number of steps of the output voltage Vout is relatively small when the total resistance of the dividing resistors R.sub.0 to R.sub.16 is set to R.sub.T and the resistance between the voltage dividing node selected by the switching elements S.sub.1 to S.sub.16 and the ground potential node Vss is R.
However, the number of voltage dividing resistors increases as the number of output steps increases, the number of decoder circuits 13 for controlling the switching elements S.sub.1 to S.sub.16 for selection of the voltage dividing node increases and the pattern occupying area is increased. For example, if 32 output voltages are required, it is necessary to prepare 33 voltage dividing resistors and 32 5-input decoder circuits for decoding 5-bit digital data. Generally, when the number of steps of the output voltage is 2.sup.N, it is necessary to form 2.sup.N resistive dividing nodes and 2.sup.N N-input decoder circuits for processing an N-bit digital input.
Therefore, if the value of N becomes larger, the numbers of decoder circuits and resistor elements rapidly increase and the pattern occupying area is increased, thereby making it difficult to design the circuit. In addition, since the degree of freedom of pattern change is low, it is difficult to cope with a variation in the resistance caused in the manufacturing process and it is difficult to change the design for adjustment of the resistance.
In order to solve the above problem, some decoding systems for directly decoding a digital input by use of a combination of resistors without using the decoder circuits are proposed. For example, a current-scaling type D/A converter circuit, voltage-scaling type D/A converter circuit, weighted resistor type D/A converter circuit are proposed. Among them, the current-scaling type D/A converter circuit is most frequently used.
FIG. 2 shows a known current-scaling type D/A converter circuit (refer to "Introduction to Illustrated D/A Converter by Toshikazu Yoneyama, Ohmsha, 1993", for example). Generally, the current-scaling type D/A converter circuit includes a resistor network having two types of resistors (resistances R and 2R) connected in a ladder form, n switching elements whose switching states are controlled by n-bit digital data and an operational amplifier. That is, nine resistors R each having a resistance R are serially connected, one end of the series-connected resistors R is applied with a reference potential V.sub.R, and the other end thereof is connected to a Vss node to which a ground potential Vss (0V) is applied. One-side ends of the resistors R are respectively connected to one-side ends of 8 resistors 2R each having a resistance 2R to form an R-2R type ladder resistor circuit network. The other ends of the 8 resistors having the resistance 2R are connected to switching elements S.sub.1 to S.sub.8, one switching terminal of each of the switching elements S.sub.1 to S.sub.8 is connected to the inverting input terminal (-) of the operational amplifier 11 and the other switching terminal thereof is connected to the Vss node. A feedback resistor Rf with a resistance R is connected between the inverting input terminal (-) of the operational amplifier 11 and a variable potential output node and the non-inverting input terminal (+) thereof is connected to the Vss node. The operational amplifier 11 functions to hold the voltage of the inverting input terminal (-) (common connection node B) at 0V.
In the ladder resistor circuit network, attention is paid to a connection node a.sub.8 in the resistor string (series-connected resistors R between the reference potential node V.sub.R and the Vss node). The resultant resistance when viewing the ground potential Vss side from the connection node a.sub.8 becomes R+R=2R, and the resistance when viewing the resistor 2R side (switching element side) from the connection node a.sub.8 and the resultant resistance when viewing the ground potential Vss side become 2R and are equal to each other.
Therefore, if a current flowing from the reference potential V.sub.R side into the connection node a.sub.8 is set to I.sub.7, a current I.sub.8 ' flowing from the connection node a.sub.8 towards the resistors 2R and a current I.sub.8 flowing into the ground potential Vss side are equal to each other and the following equation is obtained. EQU I.sub.8 '=I.sub.8 =I.sub.7 /2
Next, attention is paid to a connection node a.sub.7 which is directly adjacent to the connection node a.sub.8 of the resistor string on the reference potential V.sub.R side and the resultant resistance when viewing the ground potential Vss side from the connection node a.sub.7 becomes 2R as shown by the following equation. ##EQU1##
Therefore, since the resultant resistance when viewing the ground potential Vss side from the connection node a.sub.7 and the resistance when viewing the resistor 2R become 2R and are equal to each other, a current I.sub.6 flowing from the reference potential V.sub.R side is equally divided into a current I.sub.7 ' flowing towards the resistor 2R side and a current I.sub.7 flowing towards the ground potential Vss side and the following equation is obtained. EQU I.sub.7 '=I.sub.7 =I.sub.6 /2
As described above, if attention is sequentially paid to the connection nodes of the resistor string in an order towards the reference potential V.sub.R side, the resultant resistance when viewing the ground potential Vss side from each connection node can be expressed by the continued fraction indicated by the following equation and becomes equal to the resistance when viewing the resistor 2R. ##EQU2##
Therefore, in each connection node, a current flowing from the reference potential V.sub.R side is equally divided into a current flowing towards the resistor 2R side and a current flowing into the ground potential Vss side.
That is, if a current flowing from the reference potential V.sub.R into the resistance circuit network is set to I.sub.0, currents flowing from the respective connection nodes sequentially set in an order from the reference potential V.sub.R side to the ground potential Vss side in the resistor string into corresponding switching elements S.sub.1 to S.sub.8 are sequentially weighted with I.sub.0 /2, I.sub.0 /4, I.sub.0 /8, . . . , I.sub.0 /2.sup.N.
Then, currents flowing into the common connection node B of the switching elements S.sub.1 to S.sub.8 are added in the operational amplifier 11 and converted into a voltage and thus a D/A conversion output (variable output potential) Vout can be obtained.
Further, the current I.sub.0 flowing from the reference potential V.sub.R into the resistance circuit network is expressed by the following equation . EQU I.sub.0 =-V.sub.R /R
Therefore, the D/A converter output voltage Vout can be obtained as follows and expressed by the product of the reference potential V.sub.R and the digital input. ##EQU3##
As described above, in the current-scaling type D/A converter circuit shown in FIG. 2, the switching element group connected to the resistance circuit network is directly controlled by the digital input and since a large number of digital decoder circuits as is required in the circuit shown in FIG. 1 are not necessary, the pattern occupying area can be reduced. Further, since the number of types of the unit resistances used in the resistance circuit network is small (two types having resistances of R and 2R), the circuit design can be easily made. Particularly, this is an effective system when the number n of bits of the digital input becomes larger.
However, if the current-scaling type D/A converter circuit of FIG. 2 is directly used in the power supply potential generating circuit, a problem occurs by the following two reasons.
(1) Since an output voltage Vout obtained after D/A conversion is a negative potential and a negative power supply potential is necessary, it is impossible to generate a positive variable potential which is normally used.
(2) The number of unit resistors R and 2R of the resistor circuit network increases (in the above example, the digital input is 8 bits, and nine resistors with the resistance R and eight resistors with the resistance 2R are used) as the number n of bits of the digital input increases, and it becomes necessary to use resistors with a high resistance in order to reduce the power consumption in the case of a circuit operated in the standby mode. As a result, since the pattern occupying area of the resistors R and 2R becomes extremely larger in comparison with the resistive voltage dividing system which is simple in construction, the pattern occupying area of the whole D/A converter circuit cannot be reduced even if the decoder circuits can be made unnecessary.